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synchronous equipment stratum 3/3e clock unit ? SY10 raltron electronics corp. 10651 n.w.19 th st florida 33172 u.s.a. tel: 305 593-6033 fax: 305-594-3973 e-mail: sales@raltron.com internet: http://www.raltron.com 1 SY10 date: august 30, 2002 ? introduction the SY10 - an accurate time and frequency source that had been designed as a subsystem level module. the module is designed to work within atm, sonet, sdh, and wireless systems where synchronization is vital. the SY10 is an excellent synchronization solution for timing, with jitter and wander compliance per the specified within itu-t recommendations g.812/g.813 and bellcore gr-1244-core. the SY10 is an enhanced version of sy01 and is designed for stratum 3 and stratum 3e, but also holds certain features that can make it useful for sonet minimum clock (smc) or other kinds of system clocks. ? features a synchronization solution for timing, jitter and wander concerns in a single module. complies with itu-t recommendations g.812/813 and bellcore gr-1244-core for stratum 3 and stratum 3e applications. supports modes of operation: locked, holdover and free-run. accepts reference inputs from up to six independent sources from 8khz to 77.76mhz provides up to 3 output from 8khz to 77.76mhz (two user select and one fixed at 8khz) loop filtering utilizing specific software application in the digital signal processor (dsp). continuously monitors and evaluate input reference signals. phase build-out for output clock. creates a history buffer for holdover mode operation. alarm and status signals and messages. host interface spi for configuring and remote monitoring. supports master/slave configuration of two SY10 with minimum phase error between two clocks. provides ?hit-less? switching during switching between the clocks. pin compatible with 18 pins sy01 module. small dimensions of 1.82 x 1.82 x 0.7 inch. (0.60 inch with no mechanical cover) ? application the SY10, a synchronous equipment clock (sec), fulfills clock regeneration function for stratum 3 and 3e equipment for: atm, sdh, pdh, and sonet networks. it was designed for network system manufacturers such as: access switches, core switches, cross connects, digital multiplexers-exchangers, and sdh/sonet equipment. the unit is also suitable for pcs, wll, and wireless base stations. wherever a timing unit with high performance specifications is required, the SY10 can be embedded within the network system and provide all necessary frequencies and interfaces.
synchronous equipment stratum 3/3e clock unit ? SY10 raltron electronics corp. 10651 n.w.19 th st florida 33172 u.s.a. tel: 305 593-6033 fax: 305-594-3973 e-mail: sales@raltron.com internet: http://www.raltron.com 2 figure 1. - the functional block diagram of SY10. ? description the SY10 synchronization module is a digital pll (dpll), which utilizes application specific software in the digital signal processor (dsp). the dsp is complemented by fast hardware logic (fpga) where all multiplexers, counters, dividers, phase detectors, output frequency converters and other control logic circuits are completely implemented. the functional block diagram with maximum configuration is shown in figure 1. the module has three phase lock loop ? primary pll, secondary and utility pll. the primary pll utilizes a direct digital synthesis (dds) technique combined with a high stability ocxo in order to provide an accurate and fast dpll response and eliminates the requirement for an ocxo with high pullability. the primary loop is a low bandwidth loop that filters a major part of the wander and the jitter at the input. the output of the primary pll is connected to the secondary pll synthesizer that is also a dpll but with a wider loop bandwidth. the secondary pll loop has also another input that comes from the sec in pin. depending on the master?slave mode, the secondary loop utilizes either one of the inputs. the output of secondary pll is connected to the utility pll that is an analog phase lock loop. - the outputs of secondary and utility pll provide three independent output signals. - the spi serial communication interface provides a flow of messages between the module and a host processor. - the jtag interface provides an easy access for future software upgrade re-programming without removing the module from the system. the SY10 software provides several features such as: - switching between the references inputs on the basis of monitoring and estimation of the input signals and internal state diagram; - real time calculation of the filtering algorithm for jitter and wander in according to the approved standards; - alarm, status and messaging functions using output pins and serial communication port. for other configurations, please contact raltron. the module operates in the following three timing modes: free-run in this mode, the unit is unlocked to either of the inputs. the accuracy of the output frequencies in this mode is 4.6ppm. free-run mode is typically used when a master clock source is required, not valid history of data for the holdover mode, or immediately following system power-up before network synchronization is achieved. in the free- run mode, the SY10 provides timing and synchronization signals that are based on the accuracy of on-board oscillators only, and are not synchronized to the reference signals. holdover mux, fpd, counters & logic dsp (ram, flash) dds spi ocxo jtag control inputs ex.ref.2 ex.ref.1 alarms and statuses out 1 out 3 out 2 ex.ref.3 ex.ref.4 ex.ref.5 ex.ref.6 output pll synthesizer
synchronous equipment stratum 3/3e clock unit ? SY10 raltron electronics corp. 10651 n.w.19 th st florida 33172 u.s.a. tel: 305 593-6033 fax: 305-594-3973 e-mail: sales@raltron.com internet: http://www.raltron.com 3 in this mode, the module has lost its reference inputs and is utilizing stored timing data, called history, to control the output frequency. holdover mode is typically used while the network synchronization is temporarily disrupted. in holdover mode, the SY10 provides timing, based on data from the history buffer, while unlocked to an external reference signal. the history data is determined while the device is locked to an external reference signal. the stability of the output signal in holdover mode depends primarily on the stability of on-board oscillator and environment effects where the clock is mounted. the SY10 uses an ocxo as an on-board oscillator but other types of oscillators are available. locked to reference in this mode, the output of the module is phase locked to any of input references. the output frequency tracks the selected input reference. the ?locked to reference modes? is typically used when a slave clock source is synchronized to the network. in these modes, the SY10 provides timing signals, which are synchronized, to one of six references inputs (ref1 to ref6). the input reference signals may have a variety of nominal frequencies, which are typically specified by the end user. when the modes are selected the unit goes through a reference evaluation, and then a frequency acquisition, and finally to phase locking. local reference oscillator depending on the type of clock, a local reference oscillator is selected. for example: for a stratum 3e type of clock, the local oscillator is a high stability sc-cut ocxo that meets this standard requirements for frequency drift and jitter noise. input references the SY10 module accepts six input references ex ref1 to ex ref6. end users can specify the frequencies within a range of 8 khz to 77.76 mhz. the input reference signals are hcmos/ttl levels with timing characteristic in accordance with bellcore gr-1244-core 3.2.1.r3-1 or equivalent standards. please note that the end user must specify the input frequencies at the time of order. monitoring and evaluation of the input references using an advanced algorithm the input references are continuously monitored and evaluated by the module. there are three techniques used in the algorithm for each of reference, presence of the reference, frequency offset during the time when the unit is phase locked to the reference, and frequency offset when the unit in not phase locked to the reference. the SY10 rejects all reference signals whose frequency accuracy is offset by more than 13 ppm. at any given event that requires a switching in the operation mode, the timing module unit performs a reference evaluation test of the new target reference. since such evaluation is a continuous process, the switching takes very short time (typically less then a second). providing a successful evaluation, the unit switches to frequency and phase locking mode. on the other hand, if the reference was not qualified the unit switches to a holdover mode. filtering in the dpll the SY10 dynamically changes its loop bandwidth according to the status of the dpll. in the primary pll there are five stages that the dpll goes through before phase lock mode is achieved. the first stage is frequency acquisition that takes place until the frequency becomes equal to the reference. the second stage is the phase acquisition stage that takes place until a new phase reference is acquired. the other stages are tracking stages (1, 2 and 3) (hint: the dpll is locked and tracks the phase reference with a very low loop bandwidth). this method of three tracking stages ensures minimum locking time and minimum phase jumps and shifts during acquisition or transition. it also provides phase build-out during switching or rearrangement. the secondary pll operates similarly to the primary pll with an exception of a wider bandwidth (hint: it has only three stages) ? the first is frequency acquisition, second is phase acquisition and third one is tracking mode. please see detail in state diagram. history buffer for holdover mode frequency and timing data is continuously collected in the history buffer during the time when the unit is locked to any of the input references. the history buffer is actually a circular buffer in memory that keeps valid data for holdover mode during the last 90 seconds of operation. when the SY10 enters to holdover mode the data
synchronous equipment stratum 3/3e clock unit ? SY10 raltron electronics corp. 10651 n.w.19 th st florida 33172 u.s.a. tel: 305 593-6033 fax: 305-594-3973 e-mail: sales@raltron.com internet: http://www.raltron.com 4 from the buffer is validated and processed. the history buffer can be cleared by writing one to bit hlrst in cfg2 register. output signals the SY10 module provides three output signals out, opt out1 and opt out2. the outputs are generated by the internal oscillators vcxo and scaled by the output frequency converters. two vcxo oscillators can be used per module providing two independent frequency types and the third one (opt out2) is derived from one of them. the performance of the module significantly depends on the output oscillator and special care is taken to define their specifications. the used vcxo are high quality crystal oscillators with very low output jitter. the frequency of the oscillator is specified according to the network application where the SY10 will be used. the frequency converters divide signal from the oscillator to the specified frequencies. indications the SY10 provides detailed monitoring and indication of operation of the unit. two types of monitoring and status indicating are provided: - visual indication: using ten on board color mounted led?s that indicate the operating mode of the SY10. the led indicators are mainly placed for system troubleshooting, and testing. - electronic indications: using ten digital outputs that report status and alarms from the SY10. these alarms are mainly used for communication between the module and network equipment. the internal led indicators are: signal led holdover super light red led, on when the module is in holdover mode. ref1 green led, on when the module is locked to reference 1. ref2 green led, on when the module is locked to reference 2. ref3:. green led, on when the module is locked to reference 3 ref4: green led, on when the module is locked to reference 4. ref5 green led, on when the module is locked to reference 5. ref6 green led, on when the module is locked to reference 6. freerun orange led, on when the unit is in free running mode. unlock red led, on when the module is not locked to the selected reference signal. alarm red led, on when there is an alarm in the module
synchronous equipment stratum 3/3e clock unit ? SY10 raltron electronics corp. 10651 n.w.19 th st florida 33172 u.s.a. tel: 305 593-6033 fax: 305-594-3973 e-mail: sales@raltron.com internet: http://www.raltron.com 5 control several controls pins are available for the user to control the operation of the SY10 primary pll. the three external inputs cnt1, cnt2 and cnt3 provide the feature to change the state of operation. below, the truth table shows behavior of the SY10 module according to the control inputs states. cnt3 cnt2 cnt1 mode of operation 0 0 0 free-run 0 0 1 locked to ref1 0 1 0 locked to ref2 0 1 1 holdover 1 0 0 locked to ref3 1 0 1 locked to ref4 1 1 0 locked to ref5 1 1 1 locked to ref6 to change the operation of secondary pll (master-slave) can be change using ms/fr control pin. ms/fr? mode of operation 1 (or open) master (default) 0 slave ?see explanation about ms/fr below. the state of operation can be set and changed also using serial communication port, please see below. the SY10 state machine ? primary pll the state machine of SY10 module can be controlled using one of two interfaces: 1) three external control pins cnt1, cnt2 and cnt3. 2) setting bits (con0, con1, con2 and con3) in cfg1 register using serial peripheral interface (spi). after the reset the module is set to use three external control pins for control function but user can change it by setting bit ui in register cfg1. by setting the ui bit to 1 the module ignores states of the control pins and use bits in cfg1 register for state engine control. on the figure below is shown simplified stated diagram of SY10 module. figure 2 ? the SY10 state diagram ? primary pll. free run reference switching freq. and phase locking holdover 1 4 23 5 6 7 8 9 10 11 12 13 14
synchronous equipment stratum 3/3e clock unit ? SY10 raltron electronics corp. 10651 n.w.19 th st florida 33172 u.s.a. tel: 305 593-6033 fax: 305-594-3973 e-mail: sales@raltron.com internet: http://www.raltron.com 6 1) (freerun) the path 1 runs until control signals (cnt1,2,3 pins or con0,1,2,3 bits in cfg1 register) are set to zero or there is no valid history available on the acquisition buffer for the holdover. 2) (freerun_ reference_switching) the path 2 runs when there was any change at control signals. 3) (reference_switching_freerun) the path 3 runs when the control signals were changed to zero ? the free-run mode was selected. 4) (reference_switching) the path 4 runs until appropriate reference was selected. if the unit is in auto switching mode (bit autoen in cfg2 register set to 1) the module will switch in the following conditions: 1) if a reference that was selected by control signals, 2) if the selected reference is not available it will switch based on priority table (registers pr1 ? pr4). 3) if any of the references are not available it will go to holdover (path 8) if the unit is in manual switching mode (bit autoen in cfg2 register set to 0) the module will switch in following conditions: 1) if a reference that was selected by control signals, 2) if the selected reference is not available it will go to holdover (path 8) 5) (freq&phase_locking_freerun) the path 5 runs when the control signals were changed to zero ? the free-run mode was selected. 6) (holdover_freerun) the path 6 runs when the control signasl were changed to zero ? the free-run mode was selected or there is no valid history available on the acquisition buffer for the holdover. 7) (reference_switching_freq&phase_locking) the path 7 runs when the reference switching was successfully finished ? a reference was qualified and no changes at control signals. 8) (reference_switching_holdover) the path 8 runs if the following conditions: 1) if control signals were changed to one (0011) ? the holdover mode was selected. 2) if the module is in auto switching mode (bit autoen in cfg2 register set to 1) the module will switch to the holdover if none of the reference are available. 3) if the module is in manual switching mode (bit autoen in cfg2 register set to 0) and selected reference was not qualified or reference was lost during process of evaluation. 9) (freq&phase_locking_reference_switching) the path 9 runs in the following conditions: 1) if another reference was selected changing control signals. 2) if the module is in auto switching mode (bit autoen in cfg2 register set to 1) the module will switch to the reference switching if at least one of the references is available and when the currently selected reference is failing. 3) if the unit was set to operate in revertive mode (bit reven in cfg2 register is set to 1) and previously lost reference is back the module will switch to reuse the same reference. 10) (holdover_ reference_switching) the path 10 runs in the following conditions: 1) current selected reference was reacquired or if the other reference was selected changing control signals. 2) if the unit was set to operate in revertive mode (bit reven in cfg2 register is set to 1) and previously lost reference is back the module will switch to reuse the same reference.
synchronous equipment stratum 3/3e clock unit ? SY10 raltron electronics corp. 10651 n.w.19 th st florida 33172 u.s.a. tel: 305 593-6033 fax: 305-594-3973 e-mail: sales@raltron.com internet: http://www.raltron.com 7 11) (freq&phase_locking) the path 11 runs until the frequency acquisition or the phase locking is in progress with no changes at control pins. the module goes through a few intermediate states in order to accomplish phase tracking. there are three basic intermediate steps that include frequency acquiring, phase acquisition and tracking. tracking can have additional steps depending of the bandwidth to be achieved. 12) (holdover) the path 12 runs until the holdover mode is in progress with no changes at control signals. 13) (freq&phase_locking_ holdover) the path 13 runs in following conditions: 1) if the used reference was lost or was detected bad, 2) if the control signals were changed to one (0011) ? the holdover mode was selected. 14) (freerun_holdover) the path 14 runs only if the control signals were changed to one (0011) and valid history buffer for holdover operation is available ? the holdover mode was selected. SY10 master-slave operation ? secondary pll in systems where clock redundancy is required it is possible to connect two SY10 ? such connection shown at the figure below. the module has two pins dedicated for this feature ? ms/fr and sec in. the ms/fr control input selects if the module will operate as master (logic high) or slave in the system. the sec in is input for signal that comes from another clock module. in the system always clock ?one? operates as master and the second one as slave clock. when operating as a slave the output of SY10 also tracks the master so it provides minimum phase difference between the two clocks. this is very useful as it makes easier ?hitless? switching of references. the master-slave control can also be done using spi communication setting the bit ms in register cfgreg1. please see more in memory mapped registers section. the typical master-slave connection block diagram is show on figure below. figure 3. - the master ? slave connection of two SY10. the state machine of SY10 master ?slave operation module can be controlled using one of two interfaces: 3) one external control pin ms/fr. 4) setting ms bit in cfg1 register using serial peripheral interface (spi). after the reset the module is set to use the external control pin for control function but user can change it by setting bit ui in register cfg1. by setting the ui bit to 1 the module ignores states of the control pins and use bits in cfg1 register for state engine control. on the figure below is shown simplified stated diagram of SY10 master ?slave operation. SY10 1 SY10 2 sec in (pin 25) sec in (pin 25) out (pin 10) out (pin 10) m/s m/s
synchronous equipment stratum 3/3e clock unit ? SY10 raltron electronics corp. 10651 n.w.19 th st florida 33172 u.s.a. tel: 305 593-6033 fax: 305-594-3973 e-mail: sales@raltron.com internet: http://www.raltron.com 8 figure 4. - the SY10 master ? slave state diagram 1. (master) the path 1 runs until control signals ms/fr ? is set to 1 (or ms bit in cfg1 register is set to 0) or there is no valid signal at sec in pin. no valid signal means either not present or not within frequency offset window. 2. (master_slave) the path 2 runs when there was a change at ms/fr control signal from 1 to 0 (or in case of ms bit in cfgreg1 from 0 to 1) and there is valid signal at sec in pin. 3. (slave_master) the path 3 runs when there was a change at ms/fr control signal from 0 to 1 (or in case of ms bit in cfgreg1 from 1 to 0) or there is no valid signal at sec in pin (signal disappeared). 4. (slave) the path 4 runs until control signal ms/fr is set to 0 (or ms bit in cfg1 register is set to 1) and there is valid signal at sec in pin. ?see explanation below! ms/fr shared pin input since the ms/fr control input pin shares the function special caution should be taken to drive it. the signal at ms/fr signal is sampled and processed by internal software and decisions are made using following: 1) to change status of secondary pll from master to slave using ms/fr the user have to change from 1 to 0 and keep the pin logic low for period longer then 100ms not communicating through spi. if within that period of time ms/fr signal does not change level (0) and there is no clock signal at sclk pin (no changing at sclk for spi communication) the operation will be changed from master to slave. master slave 1 2 3 4 sclk ms/fr change to slave > 100ms sampes no clk signal
synchronous equipment stratum 3/3e clock unit ? SY10 raltron electronics corp. 10651 n.w.19 th st florida 33172 u.s.a. tel: 305 593-6033 fax: 305-594-3973 e-mail: sales@raltron.com internet: http://www.raltron.com 9 2) to maintain slave mode while still communicating through spi signal ms/fr should be set high prior sclk for no more then 100ms at any given time. please see timing constrains for spi communication. 3) to change status of secondary pll from slave to master the signal ms/fr should be set to high (1) for period longer then 100ms not communicating through spi. 4) to maintain master mode while still communicating through spi signal ms/fr should be set low during sclk for no more then 100ms at any given time. please see timing constrains for spi communication. changing mode of operation can be done easier using spi communication interface ? please see next paragraph. for other configuration please contact raltron electronics corp. sampes sclk ms/fr no change 100ms clk signal sclk ms/fr change to master > 100ms sampes no clk signal sampes sclk ms/fr no change 100ms clk signal
synchronous equipment stratum 3/3e clock unit ? SY10 raltron electronics corp. 10651 n.w.19 th st florida 33172 u.s.a. tel: 305 593-6033 fax: 305-594-3973 e-mail: sales@raltron.com internet: http://www.raltron.com 10 ? serial communication bus ? spi the module can be configured, controlled and monitored using an on board serial communication port ? spi provided on the SY10. there are four pins available for this features sclk, ms/fr, din and dout. the din and dout are ports used to transfer command and data in and out of the module. the sclk is input used to clock the data transfer in and out of the module and ms/fr is shared pin that provides frame synch signal. the SY10 operates only as a slave device on spi bus so the transfer of the data or command should be initiated by a micro- controller. the micro-controller can read or write to configuration registers and read only from status registers mapped internally into the SY10. optionally the interface can be implemented in spi. figure 9. - the spi serial communication communication protocol for spi the interface is synchronous peripheral interface (spi), the master must to provide clock signal and initiate the communication cycles. there are read and write cycles and each communication cycle that consists of 16 clocks (8+8 bits). data is latched every rising edge of clock input from most significant bit. the maximal allowed frequency for sclk is 10mhz - t clk . write data cycle the master sends to the module two bytes (2 x 8bits). first byte is always command byte. the second byte is the data byte contains information to write. command byte data format: 7(msb) 6 5 4 3 2 1 0(lsb) r/w x a5 a4 a3 a2 a1 a0 - a5?a0 - module register address please see the table 1. - r/w - read (1) or write (0) bit. - x ? not used. data byte format: 7(msb) 6 5 4 3 2 1 0(lsb) d7 d6 d5 d4 d3 d2 d1 d0 - d7?d0 ? content to be written to the register addressed by a5:a0 read data cycle the master sends to the module one-command byte and receives from module information byte (see 1.1 and 1.2). command byte data format: 7(msb) 6 5 4 3 2 1 0(lsb) r/w x a5 a4 a3 a2 a1 a0 - a5?a0 - module register address please see the table 1. - r/w - read (1) or write (0) bit. data byte format: cpu SY10 sclk dout din ms/fr
synchronous equipment stratum 3/3e clock unit ? SY10 raltron electronics corp. 10651 n.w.19 th st florida 33172 u.s.a. tel: 305 593-6033 fax: 305-594-3973 e-mail: sales@raltron.com internet: http://www.raltron.com 11 7(msb) 6 5 4 3 2 1 0(lsb) d7 d6 d5 d4 d3 d2 d1 d0 - d7-d0 ? content to be read from the module addressed by a5:a0 spi flowchart figure 10. - the spi flowchart . timing diagrams fetch data from mmr to send out read spistatus = ok spistatus = overflow spistatus = writeerror no spistatus = addresserror no of received bytes = 2? command read or write? y es no write read write data in mmr valid data to write in mmr? write y es no reset all spistatus = ok command read or write? y es received address valid? no of received bytes > 0? y es no of received bytes = 1? no y es no entr y p oint wait for the next byte
synchronous equipment stratum 3/3e clock unit ? SY10 raltron electronics corp. 10651 n.w.19 th st florida 33172 u.s.a. tel: 305 593-6033 fax: 305-594-3973 e-mail: sales@raltron.com internet: http://www.raltron.com 12 please see below the timing diagram for a write and read cycles. please note that dout is not a tri-state output. the minimum value for t clk is 100ns and time out t out is approximately 1sec. the spi will latch data on input din and set data on output dout on every rising edge of sclk however operation mode can be changed operates on request. changes may include clock polarity, length of data etc. during the read cycle the master have to provide a pause between two bytes of minimum 1ms (t wait 1ms). figure 11. - write cycle spi 8-bit parameter min max t clk ? clk 100ns t fs ? time to set fr prior clk transition t clk /2 t fh ? time to hold fr after clk transition t clk /2 t ds ?time to set data prior clk transition 10ns t dh ? time to hold data after clk transition 1ns figure 12. - read cycle spi 8-bit dout d5 d0 d1 d2 d3 d4 d6 d7 a 0 a 1 a 2 a 3 a 4 t clk sclk din t wait ms/fr a 0 a 1 a 2 a 3 a 4 d5 d0 d1 d2 d3 d4 d6 d7 t clk sclk din t out dout ms/fr t fs t fh t ds t dh
synchronous equipment stratum 3/3e clock unit ? SY10 raltron electronics corp. 10651 n.w.19 th st florida 33172 u.s.a. tel: 305 593-6033 fax: 305-594-3973 e-mail: sales@raltron.com internet: http://www.raltron.com 13 memory mapped registers there are twenty-eight 8-bit registers accessible through the serial port: 12 registers to write and read data and 16 registers to only read data from module. see table 1 for memory map registers and their purpose. format m l addr. read write name 7 6 5 4 3 2 1 0 description 00h y y pr1 r23 r22 r21 r20 r13 r12 r11 r10 4-bit priority for references 1-2 01h y y pr2 r43 r42 r41 r40 r33 r32 r31 r30 4-bit priority for references 3-4 02h y y pr3 r63 r62 r61 r60 r53 r52 r51 r50 4-bit priority for references 5-6 03h y y pr4 x x x x x x x x not used 04h y n rfh1 s7 s6 s5 s4 s3 s2 s1 s0 ref. 1 frequency shift in ppm 05h y n rfh2 s7 s6 s5 s4 s3 s2 s1 s0 ref. 2 frequency shift in ppm 06h y n rfh3 s7 s6 s5 s4 s3 s2 s1 s0 ref. 3 frequency shift in ppm 07h y n rfh4 s7 s6 s5 s4 s3 s2 s1 s0 ref. 4 frequency shift in ppm 08h y n rfh5 s7 s6 s5 s4 s3 s2 s1 s0 ref. 5 frequency shift in ppm 09h y n rfh6 s7 s6 s5 s4 s3 s2 s1 s0 ref. 6 frequency shift in ppm 0ah y n rfh7 x x x x x x x x not used 0bh y n rfh8 x x x x x x x x not used 0ch y n rst1 s41 s40 s31 s30 s21 s20 s11 s10 references 1-4 status 0dh y n rst2 x x x x s61 s60 s51 s50 references 5-6 status 0eh y n psp1 ps7 ps6 ps5 ps4 ps3 ps2 ps1 ps0 status of primary pll 0fh y n psp2 us3 us2 us1 us0 ss3 ss2 ss1 ss0 status of secondary and utility pll 10h y y pmax s7 s6 s5 s4 s3 s2 s1 s0 maximum frequency pull in ppm 11h y y pmin s7 s6 s5 s4 s3 s2 s1 s0 minimum frequency pull in ppm 12h y y cfg1 ui x x ms con3 con2 con1 con0 configuration 1 13h y y cfg2 x x p f r h r a configuration 2 14h y y fa1 f7 f6 f5 f4 f3 f2 f1 f0 frequency acquisition set for pll1 15h y y bw11 p13 p12 p11 p10 p03 p02 p01 p00 bandwidth 1 and 0 set for pll1 16h y y bw12 p33 p32 p31 p30 p23 p22 p21 p20 bandwidth 3 and 2 set for pll1 17h y y fb2 f3 f2 f1 f0 b3 b2 b1 b0 frequency acquisition (f) and bandwidth track (b) for pll2 18h y n sst st7 st6 st5 st4 st3 st2 st1 st0 spi status register 19h y n cid cid7 cid6 cid5 cid4 cid3 cid2 cid1 cid0 customer id register 1ah y n sid sid7 sid6 sid5 sid4 sid3 sid2 sid1 sid0 software id register 1bh y n hid hid7 hid6 hid5 hid4 hid3 hid2 hid1 hid0 hardware id register table 1. memory map registers. reference priority registers (pr1 to pr4) ? address 00-03h there are four registers pr1 ? pr4 that specify priority during switching. every reference has 4-bit priority so two references are defined per register. the priority means that the module in the event of loosing reference will lock to valid reference with higher priority available if bit autoen of register cfg2 is set to one. the initial priority is set by module but can be overridden by customer. the highest priority is 1111b and the lowest priority is 0001b. if priority is set to zero (0000b) the reference will not be used in the module ? the status will be ?reference present but not in use?. - r10-r13 ? defines reference 1 priority - r20-r23 ? defines reference 2 priority - r30-r33 ? defines reference 3 priority - r40-r43 ? defines reference 4 priority - r50-r53 ? defines reference 5 priority - r60-r63 ? defines reference 6 priority the default values are: pr1:0x78h pr2:0x56h pr3:0x34h pr4:0x12h frequency shift registers (rfh1-rfh8) - address 04-0bh.
synchronous equipment stratum 3/3e clock unit ? SY10 raltron electronics corp. 10651 n.w.19 th st florida 33172 u.s.a. tel: 305 593-6033 fax: 305-594-3973 e-mail: sales@raltron.com internet: http://www.raltron.com 14 the registers indicate how far the references out of nominal frequency in parts per million (ppm). the resolution is 0.5ppm. the range is 63ppm. if the frequency above or below 63ppm range, the +63 or -63 is shown respectively and proper status indicated in reference status registers. the format is 2-s compliment and for example if the content of rfs3 register is 11000111 then the third reference is: -28.5ppm 7(msb) 6 5 4 3 2 1 0(lsb) sign 2 5 2 4 2 3 2 2 2 1 2 0 2 -1 the default values are: rfh1: 0xffh rfh2: 0xffh rfh3: 0xffh rfh4: 0xffh rfh5: 0xffh rfh6: 0xffh rfh7: 0xffh rfh8: 0xffh reference status registers (rst1-rst2) - address 0c-0dh there are 2 reference status registers that hold information about status of references. each reference has 2-bit status or each register keep statuses for four references. the possible statuses are: binary number status description 00 not present reference not present or can not be evaluated 01 present reference present but out of frequency range 10 not in use reference present but not in use 11 reference ok reference present and in the frequency range - s10-s11 ? defines status of reference 1 - s20-s21 ? defines status of reference 2 - s30-s21 ? defines status of reference 3 - s40-s41 ? defines status of reference 4 - s50-s51 ? defines status of reference 5 - s60-s61 ? defines status of reference 6 the default values are: rst1: 0x00h rst2: 0x00h pll status registers (psp1-psp2) - address 0e-0fh register psp1 indicates status of primary pll. in the register the 4 least significant bits indicate status of the pll and the 4 most significant bits indicate reference in use in the loop. the possible statuses of primary pll are shown in psp1: ps3-ps0 status description 0000 pll not locked. this status represents major error. 0001 frequency acquisition 0010 phase acquisition 0011 tracking bandwidth 0 0100 tracking bandwidth 1 (sp1 only) 0101 tracking bandwidth 2 (sp1 only) 0110 tracking bandwidth 3 (sp1 only) 0111 phase build-out 1000 holdover 1001 free run the possible reference bits are: ps7-ps4 status description x000 no reference in use (module in free run or holdover) x001 reference 1
synchronous equipment stratum 3/3e clock unit ? SY10 raltron electronics corp. 10651 n.w.19 th st florida 33172 u.s.a. tel: 305 593-6033 fax: 305-594-3973 e-mail: sales@raltron.com internet: http://www.raltron.com 15 x010 reference 2 x011 reference 3 x100 reference 4 x101 reference 5 x110 reference 6 0xxx holdover history buffer not available 1xxx holdover history buffer available register psp2 indicates status of secondary pll. in the register the 4 least significant bits indicate status of the secondary pll and the 4 most significant bits indicate status of the utility pll if available. ss3-ss0 status description 0000 pll not locked. this status represents major error. 0001 frequency acquisition operating as a master clock 0010 phase acquisition operating as a master clock 0011 tracking bandwidth operating as a master clock 0100 frequency acquisition operating as a slave clock 0101 phase acquisition using operating as a slave clock 0110 tracking bandwidth using operating as a slave clock the possible utility pll status bits. us3-us0 status description 0000 not locked 0001 locked the default values are: psp1: 0x00h psp2: 0x00h frequency pull range registers (pmax and pmin) - address 10-11h these registers specify the window of pull-in range and reference acceptance frequency window. the pmax register specifies maximum frequency window that the module can be locked on and frequency beyond references will be rejected. the pmin registers frequency window within references will be accepted. the pmax must be greater then pmin and both are positive numbers. the data format is unsigned binary 8-bit number, for example if the content of pmax register is 00011110 and pmin 00011010 then the pull in range is: 15ppm and reference acceptance is 13ppm: 7(msb) 6 5 4 3 2 1 0(lsb) 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 -1 the default values are: pmax: 0x1eh pmin: 0x1ah configuration registers (cfg1 and cfg2) - address 12-13h register cfg1 used to set clock mode of operation. the user can select which interface will be used to change the mode of operation by setting bit ui. if the ui bit in cfg1 register is set to 0 (default) the module will change the state in according to three input pins cnt1, cnt2 and cnt3. if the if the ui bit in cfg1 register is set to 1 the module will changed the state in according to four bits (con0, con1, con2 and con3) in cfg1 registers. there are 4 bits to set 10 modes of operation: con3 con2 con1 con0 mode of operation 0 0 0 0 free-run 0 0 0 1 lock to reference 1 0 0 1 0 lock to reference 2 0 0 1 1 holdover 0 1 0 0 lock to reference 3 0 1 0 1 lock to reference 4
synchronous equipment stratum 3/3e clock unit ? SY10 raltron electronics corp. 10651 n.w.19 th st florida 33172 u.s.a. tel: 305 593-6033 fax: 305-594-3973 e-mail: sales@raltron.com internet: http://www.raltron.com 16 0 1 1 0 lock to reference 5 0 1 1 1 lock to reference 6 1 1 1 0 not used 1 1 1 1 not used other combinations are not supported and ignored. bits 7 to 4 of cfg1 are reserved for future use and ignored in this set. bit ms in cfg1 sets the module to master ? slave operation, ms bit 0 (default) the module operates as master and ms bit 1 the module operates as slave in condition that a signal at sec in (pin 25) is present. register cfg2 used by customer to control behavior of the module for application needs. 7(msb) 6 5 4 3 2 1 0(lsb) x x pbd frev reset hlrst reven autoen autoen - when set to logic high, enabling automatic switching to other reference in the event of loosing current reference according to priority set by registers pr1-pr4. when set to logic low, will not switch to other reference. reven - when set to high, will enable revertive operation. hlrst - when set to high, will erase previous operation history for holdover. reset - when set to high, will initiate internal reset of the module. frev ? when set to high and if autoen set to high will switch references based on their frequency offset (select the best of available). pbd - when set to high phase build out is disabled. the default values are: cfg1: 0x00h cfg2: 0x00h frequency acquisition set for primary pll (fa1) - address 14h fa1 register determines the bandwidth during frequency acquisition of pll. the values of fa0-7 represent frequency acquisition in hz (0-256hz). the default values are: fa1: 100 bandwidth set registers for pll1 (bw11, bw12) - address 15-16h bw11 and bw12 registers determine the tracking bandwidth of the primary pll. there four sets of bits each one representing the corresponding tracking bandwidth. the table below shows the available combinations. px3 px2 px1 px0 bandwidth 0 0 0 0 na 0 0 0 1 0.001hz 0 0 1 0 0.01hz
synchronous equipment stratum 3/3e clock unit ? SY10 raltron electronics corp. 10651 n.w.19 th st florida 33172 u.s.a. tel: 305 593-6033 fax: 305-594-3973 e-mail: sales@raltron.com internet: http://www.raltron.com 17 0 0 1 1 0.1hz 0 1 0 0 1 0 1 0 1 2 0 1 1 0 3 0 1 1 1 10 1 0 0 0 20 all others tbd the default values are: bw11: 0x23h bw12: 0x01h frequency acquisition and bandwidth track for pll2 (fb2) ? address 17h fb2 register determines bandwidth for secondary pll in frequency acquisition and tracking modes. the tables below represent available combinations for b0-b3 (frequency acquisition) and f0-f3 (tracking). b3 b2 b1 b0 bandwidth f3 f2 f1 f0 bandwidth 0 0 0 0 na 0 0 0 0 na 0 0 0 1 10hz 0 0 0 1 3hz 0 0 1 0 20hz 0 0 1 0 5hz 0 0 1 1 30hz 0 0 1 1 10hz 0 1 0 0 40hz 0 1 0 0 15hz 0 1 0 1 50hz 0 1 0 1 20hz 0 1 1 0 60hz 0 1 1 0 25hz 0 1 1 1 70hz 0 1 1 1 30hz 1 0 0 0 80hz 1 0 0 0 35hz 1 0 0 1 90hz 1 0 0 1 40hz 1 0 1 0 100hz 1 0 1 0 50hz 1 0 1 1 200hz 1 0 1 1 60hz 1 1 0 0 300hz 1 1 0 0 70hz 1 1 0 1 400hz 1 1 0 1 80hz 1 1 1 0 500hz 1 1 1 0 100hz 1 1 1 1 600hz 1 1 1 1 200hz the default value: fb2: 0x53h. spi status register (sst) ? address 18h the sst register represents current status of spi communication. the address can be read only one of the following values: message value action spierrstatok 0 if correct command was received by the module spierrrecoverflow 2 if more then two bytes are received before the routine handled spierrinvalidaddr 3 if incorrect address was received by the module spierrinvalidwriteaddr 4 if incorrect write address or value was received by the module customer id register (cid) ? address 19h the cid register contains unique customer identification number. the default value: cid: 0x03h. software id register (sid) ? address 1ah the sid register contains unique software identification number.
synchronous equipment stratum 3/3e clock unit ? SY10 raltron electronics corp. 10651 n.w.19 th st florida 33172 u.s.a. tel: 305 593-6033 fax: 305-594-3973 e-mail: sales@raltron.com internet: http://www.raltron.com 18 the default value: sid: 0x18h. (will vary with new updates) the standard timing application in systems a typical timing application for telecommunication equipment is shown at the figure below. the system consists of two clock cards (cc1 and cc1) and several line cards (lc 1 to lc n). the clock cards use two clock modules SY10 to generate two redundant signal references for the whole box and the line cards use high frequency synchronizer module sy05 as a high frequency reference signals for communication ics (for e.g. transceivers). the two clock cards are connected in such a way to provide a master/slave operation of two clocks. at cc the local processors can configure and monitor SY10 module by serial port spi. two reference signals and optionally four status signals from each clock card (status 1 and status 2) are distributed to all line cards. the status 1 and 2 signals are holdover (pin 1 at SY10), freerun (pin 7), alarm out (pin 11) and pll unlock (pin 17) and they are connected to the corresponding pins at sy05 modules. for a particular application or a timing application that best fits to you please contact raltron. figure 9. a typical timing application. sy05 1 hf out 1 lc 1 sy05 2 hf out 2 lc 2 sy05 n hf out n lc n status 1 out (10) SY10 1 sec in (25) sec in (25) out (10) serial port SY10 2 status 2 serial port cc 1 cc 2
synchronous equipment stratum 3/3e clock unit ? SY10 raltron electronics corp. 10651 n.w.19 th st florida 33172 u.s.a. tel: 305 593-6033 fax: 305-594-3973 e-mail: sales@raltron.com internet: http://www.raltron.com 19 ? specifications general specifications mechanical 1.82? (d) x 1.82? (w) x 0.70? (h) 1.8? (d) x 1.8? (w) x 0.60? (h) metal box module on pcb power supply 3.3vdc warm up current supply 700ma max @ 25c varies from different oscillator used steady state current supply 400ma max. @ 25c operating temperature -20c to 70c other ranges available on request humidity 5% to 95% non-condensing internal oscillators ocxo sc-cut for stratum 3e at-cut for stratum 3 input signals number of inputs 6 input reference frequency 8khz to 77.76mhz user selectable signal level hcmos/ttl compatible time reference characteristics bellcore: gr-1244-core 3.2.1.r3-1 number of outputs 3 output 1 8khz to 77.76mhz user define output 2 8khz to 77.76mhz user define output 3 8khz output signal signal level i/o hcmos 3.3v levels 5v tolerant signal quality performance jitter tolerance bellcore: gr-1244-core 4.2 itu-t: g.813 phase transient tolerance bellcore: gr-1244-core 4.4 wander generation bellcore: gr-1244-core 5.3 itu-t: g.812 wander tolerance bellcore: gr-1244-core 4.3 itu-t: g.812 jitter generation and transfer bellcore: gr-1244-core 5.5 itu-t: g.812 wander transfer bellcore: gr-1244-core 5.4 itu-t: g.812 frequency output performance stratum 3e stratum 3 free run accuracy 4.6ppm 4.6ppm gr-1244-core 5.1 itu-t: g.812 holdover frequency stability 1x10 -8 /24 h 0.37x10 -6 /24 h bellcore: gr-1244-core 5.2 itu-t: g.812 initial offset 1x10 -9 50x10 -9 bellcore: gr-1244-core 5.2 itu-t: g.812 temperature 8x10 -9 280x10 -9 drift 1x10 -9 1x10 -9 bellcore: gr-1244-core 5.2 itu-t: g.812 phase build-out yes no bellcore: gr-1244-core 5.7 itu-t: g.812 dpll bandwidth 0.001hz 0.1hz or adjustable up to 20hz lock time <700 <100sec gr-1244-core 3.5 lock accuracy 1x10 -11 1x10 -11
synchronous equipment stratum 3/3e clock unit ? SY10 raltron electronics corp. 10651 n.w.19 th st florida 33172 u.s.a. tel: 305 593-6033 fax: 305-594-3973 e-mail: sales@raltron.com internet: http://www.raltron.com 20 ? pin assignment figure 10 ? bottom view pin # name description 1 holdover holdover signal -> the output is high when the unit is in holdover mode 2 ref 3 reference 3 signal -> see i ndication section on page 4 3 ref 1 reference 1 signal -> see i ndication section on page 4 4 ref 4 reference 4 signal -> see i ndication section on page 4 5 ref 2 reference 2 signal -> see i ndication section on page 4 6 ref 5 reference 5 signal -> see i ndication section on page 4 7 freerun free-run signal -> the output is high when the unit is in the free run mode 8 ref 6 reference 6 signal -> see i ndication section on page 4 10 m/s out master/slave synchronizing output (to be connected to slave module sec-in 11 alarm out alarm signal -> the output is high when there is an alarm in the module. 12 opt out2 optional output 2-> the secondary output of the synchronized signal 13 cnt 1 control input 1 -> the external input for selecting mode of the unit ? see table. 14 cnt 3 control input 3 -> the external input for selecting mode of the unit ? see table. 15 cnt 2 control input 2 -> the external input for selecting mode of the unit ? see table. 16 ms/fr master/slave selection or frame spi input -> to select master or slave ? master/ slave operation of two clocks or in case of using spi it is frame synch si gnal for communication. 17 pll unlock pll unlocked signal -> the output is high when the unit is not locked to any of the references 9,18,22,26,30 gnd ground 34 vcc positive voltage supply 19 dout serial data output -> spi serial communication interface data output 20 out synchronized output -> the output of the synchronized signal 21 sclk serial clock input -> spi serial communication interface clock input 23 din serial data input/ -> spi serial communication interface data input 24 opt out1 optional output 1-> the secondary output of the synchronized signal, . 25 sec in sec input -> the input from the second clock module ? master/slave operation of two clo cks. 27 ex ref 4 external reference 4 input -> the input signal from reference 4 28 ex ref 2 external reference 2 input -> the input signal from reference 2 29 ex ref 6 external reference 6 input -> the input signal from reference 6 31 ex ref 3 external reference 3 input -> the input signal from reference 3 32 ex ref 1 external reference 1 input -> the input signal from reference 1 33 ex ref 5 external reference 5 input -> the input signal from reference 5 34 33 32 31 30 29 28 27 26 1 2 3 4 5 6 7 8 9 vcc ex ref 1 gnd ex ref 2 gnd opt out1 gnd out gnd holdover ref 1 ref 2 freerun gnd alarm out cnt 1 cnt 2 pll unlock 10 11 12 15 13 14 16 17 18 19 20 21 22 23 24 25 ref 3 ref 4 ref 5 ref 6 m/s out opt out2 ms/fr cnt 3 dout sclk din sec in ex ref 4 ex ref 6 ex ref 3 ex ref 5
synchronous equipment stratum 3/3e clock unit ? SY10 raltron electronics corp. 10651 n.w.19 th st florida 33172 u.s.a. tel: 305 593-6033 fax: 305-594-3973 e-mail: sales@raltron.com internet: http://www.raltron.com 21 ? mechanical dimensions figure 11 ? the mechanical dimensions. figure 11 shows the mechanical dimension of the SY10 module. the module can be supplied in two different types of packaging: - metal box - module without packaging the label on the module shows part number, factory name, week and year of production. without metal cover maximum height reaches 0.60?. (0.76) 1.82 sq. 1.60 marking area 1 18 34 1 17 .100 1.400 .005 .210 (40.64) (35.56 .127) (4.57) (46.23 sq.) (2.54) 1.700 (43.18) pcb .085 (2.16) .100 (2.54) .060 (1.52) (4 plcs) .910 (23.11) c l l c unless otherwise specified, all tolerances are: .005 (.127 mm). notes: .910 (4 plcs) .200 (5.08) .065 (1.65) .076 (1.93) .071 (1.82) .030 .630 (16.00) .440 (11.18)

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